Definition
Pooling PCB—also called panel sharing—is a fabrication strategy where multiple independent orders with identical stack-ups occupy a single production panel. Unlike standard panelization, which combines copies of one design for a single customer, pooling aggregates different designs that match exactly in layer count, base material (e.g., FR-4 TG150), copper weight, board thickness, surface finish (ENIG/HASL), solder mask color, and drill/routing tolerances. The core logic is simple: amortize NRE (tooling, CAM, lamination setup) across many jobs rather than one.
How It Works
1.Order Submission: Customers upload Gerbers and select “pooling” with fixed spec sets defined by the fabricator.
2.Spec Matching & Nesting: CAM engineers bin compatible orders and auto-nest them into a standard production array (e.g., 18"×24") using DFM-validated clearance rules.
3.Mass Production: A single lamination and imaging cycle runs the full panel through drilling, plating, etching, solder mask, and surface finish.
4.Depaneling & Sorting: Individual boards are routed or V-scored out, visually inspected per IPC-A-600, then sorted and packed by order ID.
Key Benefits
Cost Reduction: Setup and material waste are shared; unit pricing drops 40–70% versus standalone runs.
Faster Lead Time: Panels enter queue immediately once filled; no waiting for individual tooling.
Consistent Quality: Full IPC-compliant process control; same yield standards as volume production.
Ideal Fit: Prototypes and low-volume builds avoid minimum-order penalties while retaining production-grade reliability.
Constraints & Best Practices
Pooling mandates rigid spec uniformity—no custom stack-ups, impedance tweaks, or special requests. If the pool fails to fill, dispatch may delay until the next batch.
Design to Standard DFM: Adhere strictly to the fabricator’s published pooling design rules (annular ring, spacing, hole size).
Align with Factory Specs: Select materials and finishes explicitly listed under their pooling program; deviations force a standalone run.
Confirm Depaneling Method: Specify V-score or routing based on edge sensitivity; poor choice risks edge damage during singulation.
Typical Use Cases
Engineering validation in R&D, pre-compliance test builds, startup MVPs, hobbyist projects, and small-batch pilot runs where budget and speed outweigh customization needs.
Email: all@poe-pcba.com
Whatsapp: 85292069596
Tel: 0755-25312250/ +8613798543496
Factory Address: Floor 3, Jinyuan Industrial Park, No. 56, Tangtou Avenue, Shiyan Town, Baoan District, Shenzhen China
