PCB Manufacturing

Impedance
Controlled PCB.

Precision impedance control to ±5% standard and ±3% precision. TDR-verified test coupons on every production panel. Stackup design support included — we get the impedance right before fabrication starts.

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Single-Ended (Microstrip)

Surface trace over reference plane — standard for most digital signals

±5% / ±3%

Single-Ended (Stripline)

Buried trace between two reference planes — better shielding

±5% / ±3%

Differential Pair (Edge-Coupled)

Two traces side by side — USB, HDMI, PCIe, LVDS, DDR

±5% / ±3%

Differential Pair (Broadside-Coupled)

Two traces stacked on adjacent layers — tight coupling

±5% / ±3%

Coplanar Waveguide (CPWG)

Trace with ground planes on both sides — RF and microwave

±5% / ±3%

±3%Precision Tolerance

TDRVerified Test Coupons

5 TypesImpedance Structures

FreeStackup Design Support

Why It Matters

Signal Integrity Starts
at the PCB.

At high frequencies, a trace is not just a wire — it is a transmission line. If the impedance of that transmission line does not match the source and load, signals reflect, degrade, and cause errors. Impedance control is how you prevent that.

Getting impedance right requires precise control of trace width, dielectric thickness, and copper weight — all of which vary during fabrication. POE controls these parameters and verifies the result with TDR measurement on every production panel.

Signal Reflections & Data Errors

Impedance mismatch causes signal reflections that corrupt data. At PCIe 5.0 speeds (32 GT/s), even small impedance deviations cause bit errors that are impossible to debug without knowing the root cause.

EMI and Radiation

Uncontrolled impedance leads to signal overshoot and ringing, which increases radiated emissions. Impedance-controlled traces are a prerequisite for passing CE and FCC testing on high-speed designs.

Differential Pair Skew

Differential signals depend on both traces having identical impedance. Mismatch between the two traces of a pair causes common-mode noise and degrades the signal margin of USB, HDMI, and PCIe interfaces.

RF Performance

RF circuits are designed around specific impedance values (typically 50Ω). A coplanar waveguide or microstrip that deviates from 50Ω changes the S-parameters of your circuit and degrades antenna performance.

Our Capabilities

Impedance Control Services

Everything needed to deliver verified impedance-controlled PCBs — from stackup design to TDR measurement.

Design

Stackup Design & Impedance Calculation

We design the PCB stackup to meet your impedance targets. Dielectric thickness, copper weight, and trace geometry are all calculated using field solver software. We provide the stackup specification before fabrication begins — so you can verify it against your design.

Materials

Low-Loss & High-Frequency Materials

Standard FR4 for most digital applications. Rogers 4003C, Rogers 4350B, Isola I-Tera, and Megtron 6 for RF and high-frequency designs where dielectric constant (Dk) and loss tangent (Df) must be tightly controlled.

Verification

TDR Testing on Every Panel

Time Domain Reflectometry (TDR) test coupons are included on every production panel. We measure the impedance of each coupon and provide the test data with your order. If the impedance is out of tolerance, we do not ship.

Tolerance

±5% Standard / ±3% Precision

Standard impedance control to ±5% for most digital applications. Precision control to ±3% for RF, microwave, and high-speed serial interfaces where tighter tolerance is required. Specify your requirement when ordering.

Documentation

Impedance Test Reports

TDR measurement data provided with every impedance-controlled order. Reports include measured impedance values, target values, tolerance, and pass/fail status for each coupon. Available in PDF format for your design records.

Support

DFM Review for Impedance Designs

We review your Gerber files and stackup before fabrication. We check trace widths, spacing, reference plane continuity, and via transitions that affect impedance. Issues are flagged before production — not after.

Specifications

Impedance Control Specifications

Impedance Parameters

Parameter	Specification
Standard Tolerance	±5% of target impedance
Precision Tolerance	±3% of target impedance
Target Impedance Range	25Ω to 150Ω
Impedance Structures	Single-ended, differential, coplanar waveguide
Verification Method	TDR (Time Domain Reflectometry)
Test Coupons	Included on every production panel
Test Report	Provided with every order

PCB & Material Parameters

Parameter	Specification
Layer Count	2 to 40 layers
Standard Material	FR4, High-Tg FR4 (Dk 4.2–4.5)
Low-Loss Materials	Rogers 4003C, 4350B; Isola I-Tera; Megtron 6
Min Trace Width	3 mil standard; 2 mil advanced
Copper Weight	0.5 oz to 3 oz
Board Thickness	0.4 mm to 6.0 mm
Surface Finish	ENIG, OSP, ENEPIG, Immersion Ag/Sn

Applications

Where Impedance Control Is Required

Any interface with a defined characteristic impedance requires controlled PCB traces.

PCIe

Gen 3 / 4 / 5 / 6

85Ω differential. PCIe 5.0 at 32 GT/s requires ±3% tolerance and careful via stub management.

DDR

DDR4 / DDR5 / LPDDR5

Single-ended 40–60Ω, differential 80–100Ω. Fly-by topology requires matched impedance across all data lanes.

USB

USB 3.2 / USB4 / Thunderbolt

90Ω differential. USB4 at 40 Gbps is extremely sensitive to impedance discontinuities at connectors and vias.

HDMI

HDMI 2.0 / 2.1

100Ω differential. HDMI 2.1 at 48 Gbps requires tight impedance control and low-loss dielectric materials.

RF / MW

50Ω Systems

50Ω single-ended coplanar waveguide or microstrip. Rogers materials for low Dk/Df at GHz frequencies.

Ethernet

1G / 10G / 25G / 100G

100Ω differential. 100G Ethernet requires ±3% tolerance and careful attention to via transitions and connector launches.

LVDS

Display & Camera Interfaces

100Ω differential. Used in MIPI CSI/DSI, FPD-Link, and other high-speed display and imaging interfaces.

SERDES

High-Speed Serial Links

85–100Ω differential. Used in FPGA I/O, optical transceiver interfaces, and backplane interconnects.

Get a Quote

Start Your
Impedance PCB.

all@poe-pcba.com

+852 9206 9596

POE PCB/PCBA on LinkedIn

Do I need to specify the impedance in my Gerber files?

You need to specify the target impedance value and which nets require control. We handle the stackup design and trace width calculation. Send us your Gerber files and impedance requirements — we will confirm the stackup before fabrication.

What is a TDR test coupon?

A TDR coupon is a dedicated test structure on the PCB panel that replicates your controlled-impedance traces. We measure it with a Time Domain Reflectometer to verify the actual impedance matches your target. The coupon is cut off before delivery.

When do I need ±3% instead of ±5%?

For most digital interfaces (USB, HDMI, PCIe Gen 3), ±5% is sufficient. For PCIe Gen 5/6, 100G Ethernet, RF/microwave, and any design where signal margin is tight, specify ±3% precision control.

ImpedanceControlled PCB.

Signal Integrity Startsat the PCB.

Impedance Control Services

Stackup Design & Impedance Calculation

Low-Loss & High-Frequency Materials

TDR Testing on Every Panel

±5% Standard / ±3% Precision

Impedance Test Reports

DFM Review for Impedance Designs

Impedance Control Specifications

Where Impedance Control Is Required

Start YourImpedance PCB.

Impedance
Controlled PCB.

Signal Integrity Starts
at the PCB.

Start Your
Impedance PCB.