Definition & Purpose
A 4-layer PCB provides two internal planes (GND and PWR) between outer signal layers. Compared to 2-layer boards, it significantly improves signal integrity (SI), electromagnetic compatibility (EMI), and power distribution network (PDN) performance while maintaining moderate fabrication cost. Primary use: high-speed digital designs, mixed-signal boards, and compact consumer electronics.
Standard Stackups
Stackup A (Most Common – Signal-GND-PWR-Signal)
Layer order: Top (Sig) / L2 (GND) / L3 (PWR) / Bottom (Sig)
Functions: L2 solid GND reference for top-layer traces; L3 PWR plane paired with L2 for decoupling.
Pros: Excellent SI due to tight signal-to-ground coupling; low loop inductance; predictable controlled impedance.
Cons: Bottom-layer return paths must cross split PWR zones carefully; routing density limited by two signal layers.
Use cases: Microcontroller boards, IoT modules, high-speed interfaces up to ~5 Gbps.
Stackup B (Signal-PWR-GND-Signal)
Layer order: Top (Sig) / L2 (PWR) / L3 (GND) / Bottom (Sig)
Functions: L3 GND supports bottom signals; L2 PWR adjacent to GND for interplane capacitance.
Pros: Better thermal dissipation if PWR plane carries high current; simpler bottom-side routing.
Cons: Top-layer signals lack continuous GND reference—requires local stitching vias near signal vias crossing layers; higher crosstalk risk on top layer.
Use cases: Power-dense designs, LED drivers, motor controllers where thermal management dominates.
Stackup C (Symmetric – Sig-GND-GND-Sig)
Layer order: Top (Sig) / L2 (GND) / L3 (GND) / Bottom (Sig)
Functions: Dual solid ground planes; no dedicated power plane—power routed as polygons on signal layers.
Pros: Best EMI shielding; ultra-low impedance return paths; ideal for RF and sensitive analog.
Cons: Requires careful power distribution; no inherent plane capacitance for decoupling; increased DC IR drop if power polygons are narrow.
Use cases: RF transceivers, sensor front-ends, medical wearables.
Key Design Rules
Impedance Control
Specify trace width/spacing for target impedance (50Ω single-ended, 100Ω differential typical). Use FR-4 dielectric constant (Dk≈4.2–4.5) and thickness (5–10 mil preferred for L1-L2 coupling). Validate with field solver for edge-coupled microstrip/stripline.
EMI/SI Management
Route high-speed signals (USB, PCIe, DDR) over continuous GND planes. Never route across plane splits. Maintain return path continuity via ground stitching vias (<λ/10 spacing for critical nets). Minimize via stubs—back-drill >5 Gbps.
Plane Coupling
Maximize interplane capacitance: keep L2-L3 separation ≤10 mil (FR-4). Avoid cutouts under ICs. Decouple PWR-GND pairs with 0.1µF capacitors within 500 mil of each power pin.
Manufacturability
Use 1 oz copper for signal/power planes; 0.5 oz viable for fine-pitch routing. Minimum dielectric thickness ≥3 mil to prevent resin starvation. Confirm stackup with fabricator—some limit core/prepreg combinations.
Best Practices & Common Mistakes
Best Practices:
Place GND vias adjacent to signal vias transitioning layers.
Flood unused areas with GND copper, tie with vias every 2000 mil.
Route critical signals on top layer adjacent to solid GND.
Verify PDN impedance via DC drop analysis before layout finalization.
Common Mistakes:
Splitting GND plane for “isolation”—breaks return paths, increases loop area.
Using PWR plane as reference for high-speed signals—creates variable impedance.
Ignoring via antipads—excessive clearance enlarges loop inductance.
Specifying 4-layer without defining stackup—leaves impedance control to fab house guesswork.
Email: all@poe-pcba.com
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Tel: 0755-25312250/ +8613798543496
Factory Address: Floor 3, Jinyuan Industrial Park, No. 56, Tangtou Avenue, Shiyan Town, Baoan District, Shenzhen China
